1. Field of the Invention
The present invention relates to an image processing technology, and more particularly, to a noise reduction apparatus for image signal and method thereof.
2. Description of the Prior Art
In the field of image processing, such as television video signal processing, interference on image quality from various types of noise is a frequently confronted problem; for example, such noise types as impulse noise, spatial noise, temporal noise, and other well-known sources of noise. In general during noise processing, one dedicated circuit is adopted for detecting and suppressing noise interference contributed by each type of noise. Please refer to FIG. 1. FIG. 1 is a diagram illustrating a typical noise reduction apparatus. The noise reduction apparatus 100 has a plurality of memory devices 110, 130, 150, an impulse noise filtering circuit 120, a spatial noise filtering circuit 140, and a temporal noise filtering circuit 160. Firstly, the memory device 110 receives and stores video data in an input video signal, and the impulse noise filtering circuit 120 detects the video data stored in the memory device 110 and determines whether to perform impulse noise filtering processes upon the stored video data. If it is determined to perform, an impulse noise filtering process is performed and the processed video data is then stored in the memory device 130; otherwise, the video data is directly stored in the memory device 130 without being processed. Next, the spatial noise filtering circuit 140 detects the video data stored in the memory device 130 and determines whether to perform spatial noise filtering processes upon the stored video data. If it is determined to perform, a spatial noise filtering process is performed and the processed video data is then stored in the memory device 150; otherwise, the video data is directly stored in the memory device 150 without being processed. Lastly, the temporal noise filtering circuit 160 detects the video data stored in the memory device 150 and determines whether to perform a temporal noise filtering process upon the stored video data. If it is determined to perform, a temporal noise filtering process is performed and the processed video data is then outputted to the next stage; otherwise, the video data is directly outputted to the next stage without being processed.
Besides of the implementation as shown in FIG. 1 where every stage has its respective memory devices 110, 130, and 150, there is also another implementation of making use of a shared memory device. That is, every stage reads the video data from a shared memory device and then writes the video data back to the shared memory device after signal detecting, determining, and processing operations are finished, allowing the next stage access to the data stored in the shared memory device.
Noise detection and noise reduction processing techniques of the above-mentioned noise types, such as impulse noise, spatial noise, and temporal noise, are well known in image processing fields, and have already been discussed and disclosed in various publications, for example, in U.S. Pat. Nos. 6,385,261, 6,137,917, 4,694,342, and 6,430,318, etc. The detailed operations and principles are thus omitted herein for brevity.
In the cascade architecture as shown in FIG. 1, because the different noise detecting and processing operations are performed in a sequential and orderly fashion, it is required that the impulse noise filtering circuit 120, spatial noise filtering circuit 140, and temporal noise filtering circuit 160 have their respective and individual computing units. Moreover, because every stage of the noise filtering circuit requires a memory device for temporarily storing, or buffering, the video data of respective stages, the costs of circuit manufacturing increase. Although manufacturing costs can be reduced by adopting a shared memory architecture, the bandwidth of accessing the memory bus becomes heavily burdened due to the fact that the noise filtering circuits need to repetitively access the shared memory.